CMX644A 查看數據表（PDF） - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

CMX644A

Read Only ‘C-BUS’ Registers

REGISTER

NAME

RX DATA

BYTE

HEX

ADDRESS/

COMMAND

$EA

BIT 7

(D7)

D7

BIT 6

(D6)

D6

TONES

$EC

DETECT

1

RING

DETECT

FLAGS

RX

RING

$EF

PARITY DETECT

CHANGE

BIT 5

(D5)

D5

CALL

PRGRSS

DETECT

DETECT

BIT 4

(D4)

BIT 3

(D3)

BIT 2

(D2)

BIT 1

(D1)

D4

D3

D2

D1

CARRIER ANSWER

0

0

DETECT DETECT

RX DATA

OVER-

FLOW

RX

DATA

READY

TX DATA

UNDER-

FLOW

TX

DATA

READY

BIT 0

(D0)

D0

UN-

SCRAM

MARK

DETECT

UN-

SCRAM

MARK

RX DATA BYTE Register ($EA)

This register contains the last byte of data received. It is updated every 8 bits at the same time as the RX

DATA READY flag is set. The RX DATA BYTE register is double buffered, thus giving the user up to 8 bit

periods to read the data before it is overwritten by the next byte. Each received phase change is decoded into

2 bits (a dibit). The incoming dibits fill this register starting at the most significant end (Bits 7 and 6).

Phase change

+ 90°

0°

+ 270°

+ 180°

Dibit values

00

01

11

10

Note that the left-hand digit of the dibit will be the more

significant of the 2 bits when located in this register.

TONES DETECT Register ($EC)

This register provides information as to the presence or absence of various signalling conditions detected by

the receiver. A logic ‘1’ indicates that the signalling condition is present; a logic ‘0’ indicates that it is absent.

(Bit 7)

This bit will be set to ‘1’.

RING DETECT

(Bit 6)

Indicates the status of the Ring/Line Polarity Reversal Detector circuit.

The logic level of this bit represents the level of the internal ‘RING

DETECT’ node (see Figure 1 Block Diagram).

CALL PRGRSS DETECT

(Bit 5)

Indicates the detection of call progress tones in the selected band.

(300Hz to 620Hz or 400Hz to 620Hz).

CARRIER DETECT

(Bit 4)

Indicates the detection of a carrier in the received channel.

ANSWER DETECT

(Bit 3)

Indicates the detection of an Answer Tone of 2100Hz or 2225Hz.

(Bits 2 and 1)

These bits will be set to ‘0’.

UNSCRAM MARK

DETECT (Bit 0)

Indicates the detection of unscrambled binary one in the received data

for a period of time of 160ms.

Note that DETECT bits 5, 4 and 3 are mutually exclusive and are enabled by the setting of the DETECT

DET1 and DET0 bits (SET-UP Registers Bits 5 and 4). All of the DETECT bits in the TONES DETECT

register - except for RING DETECT (Bit 6) - require the RX PSK MODE register ENABLE bit to be set

to ‘1’.

FLAGS Register ($EF)

The flags register is used to indicate when the device requires attention. When a flag becomes set to ‘1’ and

its corresponding mask bit is ‘1’ then an interrupt (IRQN) will be generated. Immediately after the flags

register has been read, all the bits will be reset to ‘0’ and consequently any interrupt will be cleared.

© 2000 Consumer Microcircuits Limited

18

D/644A/6

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