SST89E554 查看數據表（PDF） - Silicon Storage Technology
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SST89E554 Datasheet PDF : 58 Pages
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FlashFlex51 MCU
SST89E564 / SST89V564 / SST89E554 / SST89V554
Preliminary Specifications
TABLE 2-1: PIN DESCRIPTIONS (CONTINUED) (2 OF 2)
Symbol
Type1
Name and Functions
RST
I
Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will
reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition
while the RST input pin is held high, the device will enter the External Host mode, otherwise
the device will enter the Normal operation mode.
EA#
I
External Access Enable: EA# must be driven to VIL in order to enable the device to fetch
code from the External Program Memory. EA# must be driven to VIH for internal program exe-
cution. However, Security lock level 4 will disable EA#, and program execution is only possi-
ble from internal program memory. The EA# pin can tolerate a high voltage2 of 12V
(see “Absolute Maximum Stress Ratings” on page 47).
ALE/PROG#
I/O
Address Latch Enable: ALE is the output signal for latching the low byte of the address dur-
ing accesses to external memory. This pin is also the programming pulse input (PROG#) for
the external host mode. ALE is activated twice each machine cycle, except when access to
External Data Memory, one ALE activation is skipped in the second machine cycle. However,
if AO is set to 1, ALE is disabled. (see “Auxiliary Register (AUXR)” on page 20)
XTAL1
XTAL2
I
Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal
O
clock generation circuits from an external clock source.
VDD
I
Power Supply: Supply voltage during normal, Idle, Power Down, and Standby Mode opera-
tions.
Vss
I
Ground: Circuit ground. (0V reference)
1. I = Input; O = Output
2. It is not necessary to receive a 12V programming supply voltage during flash programming.
T2-1.6 384
©2001 Silicon Storage Technology, Inc.
9
S71181-03-000 9/01 384
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