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HYS64V2200GU-8 查看數據表（PDF） - Siemens AG

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HYS64V2200GU-8

3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module

Siemens AG

HYS64V2200GU-8 Datasheet PDF : 17 Pages

First Prev 11 12 13 14 15 16 17

HYS64(72)V2200/4220GU-8/-10

SDRAM-Modules

A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module

configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence

detect protocol ( I2C synchronous 2-wire bus)

SPD-Table:

Byte#

Description

0 Number of SPD bytes

1 Total bytes in Serial PD

2 Memory Type

3 Number of Row Addresses (without BS bits)

4 Number of Column Addresses

(for x8 SDRAM)

5 Number of DIMM Banks

6 Module Data Width

7 Module Data Width (contd’ )

8 Module Interface Levels

9 SDRAM Cycle Time at CL=3

10 SDRAM Access time from Clock at CL=3

11 Dimm Config (Error Det/Corr.)

12 Refresh Rate/Type

13 SDRAM width, Primary

14 Error Checking SDRAM data width

15 Minimum clock delay for back-to-back ran-

dom column address

16 Burst Length supported

17 Number of SDRAM banks

18 Supported CAS Latencies

19 CS Latencies

20 WE Latencies

21 SDRAM DIMM module attributes

22 SDRAM Device Attributes :General

23 Min. Clock Cycle Time at CAS Latency = 2

24 Max. data access time from Clock for CL=2

25 Minimum Clock Cycle Time at CL = 1

26 Maximum Data Access Time from Clock at

CL=1

27 Minimum Row Precharge Time

28 Minimum Row Active to Row Active delay

tRRD

SPD Entry Value

128

256

SDRAM

1/2

64 / 72

LVTTL

10.0 ns

6.0 ns

none / ECC

Self-Refresh,

15.6µs

n/a / x8

tccd = 1 CLK

1, 2, 4, 8 & full page

CAS lat. = 2 & 3

CS latency = 0

Write latency = 0

non buffered/non

reg.

Vcc tol +/- 10%

10.0 ns

6.0 ns

not supported

20 ns

16 ns

2Mx64

-8

Hex

2Mx72 4Mx64

-8

4Mx72

-8

Semiconductor Group

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