HYS64V2200GU-10 查看數據表（PDF） - Siemens AG

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HYS64V2200GU-10

3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module

Siemens AG 

HYS64(72)V2200/4220GU-8/-10

SDRAM-Modules

Parameter

Symbol

Limit Values

Unit

-8

PC100

2-2-2

-8-3

PC100

3-2-3

-10

PC66

2-2-2

min. max. min. max. min. max.

Refresh Cycle

Self Refresh Exit Time

tSREX

Refresh Period (4096 cycles) tREF

10 – 10 – 10 – ns

64 – 64 – 64 – ms

Note

9)

8)

Read Cycle

Data Out Hold Time

tOH

Data Out to Low Impedance tLZ

Time

Data Out to High Impedance tHZ

Time

DQM Data Out Disable

tDQZ

Latency

3

–

3

–

3

– ns 4)

0

–

0

–

0

– ns

3

9

3

9

3

9 ns 10)

2

–

2

–

2

– CLK

Write Cycle

Data input to Precharge (write tDPL

recovery)

Data In to Active/refresh

tDAL

DQM Write Mask Latency

tDQW

2

–

2

–

2

– CLK

5

–

5

–

5

– CLK 11)

0

–

0

–

0

– CLK

Semiconductor Group

9

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