LP62E16512-I(2002) 查看數據表（PDF） - AMIC Technology

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LP62E16512-I
(Rev.:2002)

512K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Timing Waveforms

Read Cycle 1(1, 2, 4)

Address

DOUT

Read Cycle 2(1, 2, 3)

Address

CS1

CS2

HB, LB

OE

DOUT

tRC

tAA

tOH

tRC

tAA

tACS1 , tACS2

tCLZ1 , tCLZ2

tBE

tBLZ5

tOE

tOLZ5

LP62E16512-I Series

tOH

tCHZ1 , tCHZ2

tBHZ5

tOHZ5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CS1 = VIL, or CS2 = VIH , HB = VIL and, or LB = VIL.

3. Address valid prior to or coincident with CS1 and ( HB and, or LB ) transition low or CS2 transition High.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0)

7

AMIC Technology, Inc.

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