P2V28S20ATP-7 查看數據表（PDF） - Vanguard International Semiconductor

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P2V28S20ATP-7

128Mb SDRAM Specification

Vanguard International Semiconductor 

128Mb Synchronous DRAM

P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)

P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)

P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE for CKE

Current State

SELF-

REFRESH*1

CKE CKE

n-1 n

HX

/CS /RAS /CAS /WE

XXXX

Add Action

X INVALID

L H H X X X X Exit Self-Refresh (Idle after tRC)

L H L H H H X Exit Self-Refresh (Idle after tRC)

L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

L

L

X

X

XX

X NOP (Maintain Self-Refresh)

POWER

DOWN

H X X X X X X INVALID

L H X X X X X Exit Power Down to Idle

L

L

X

X

XX

X NOP (Maintain Power Down)

ALL BANKS H H X X X X X Refer to Function Truth Table

IDLE*2

H

L

L

L

L

H

X Enter Self-Refresh

H L H X X X X Enter Power Down

H L L H H H X Enter Power Down

H L L H H L X ILLEGAL

H L L H L X X ILLEGAL

H L L L X X X ILLEGAL

L X X X X X X Refer to Current State =Power Down

ANY STATE H H X X X X X Refer to Function Truth Table

other than

H L X X X X X Begin CLK Susspend at Next Cycle*3

listed above

L H X X X X X Exit CLK Susspend at Next Cycle*3

L

L

X

X

XX

X Maintain CLK Suspend

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum

setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

JULY.2000

Page-13

Rev.2.2

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