P2V28S20ATP-7 查看數據表（PDF） - Vanguard International Semiconductor
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P2V28S20ATP-7 Datasheet PDF : 51 Pages
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128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
POWER ON SEQUENCE
Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input con-
ditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
After these sequence, the SDRAM is idle state and ready
for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be pro-
grammed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.
CLK
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
V
BA0 BA1 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 LTMODE BT
BL
LATENCY
MODE
CL
000
001
010
011
100
101
110
111
/CAS LATENCY
R
R
2
3
R
R
R
R
R: Reserved for Future Use
FP: Full Page
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
BURST
TYPE
0
SEQUENTIAL
1
INTERLEAVED
JULY.2000
Page-15
Rev.2.2
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