S3067 查看數據表（PDF） - Unspecified

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S3067

MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC

Table 8. S3067 Common Pin Assignment and Descriptions

S3067

Pin Name

Level I/O Pin #

Description

SQUELCH

LVTTL I

REFCLKP

REFCLKN

DLEB

Internally I

Biased

Diff.

LVPECL

LVTTL I

LLEB

LVTTL I

KILLRXCLK

LVTTL I

SLPTIME

LVTTL I

RLPTIME

LVTTL I

RSTB

TESTEN

155MCKP

155MCKN

LVTTL I

LVTTL I

Diff.

O

LVPECL

19MCK

LOCKDET

Single O

Ended

LVPECL

LVTTL O

R16 RSCLK Clock Squelch. Active High. When SQUELCH is active

and SD is inactive, the transmit clock will be used in place of the

RSCLK.

M2 Reference Clock Input. Used as the reference for the internal bit

L3 clock frequency synthesizer.

N15 Diagnostic Loopback Enable. Active Low. Selects diagnostic

loopback. When DLEB is High, the S3067 device uses the primary

data (RSD) and clock (RSCLK) inputs. When Low, the S3067

device uses the diagnostic loopback clock and data from the

transmitter. TSD/TSCLK are active in DLEB.

N14 Line Loopback Enable. Active Low. Selects line loopback. When

LLEB is Low, the S3067 will route the data from the RSD/RSCLK

inputs to the TSD/TSCLK outputs.

M14 Kill Receive Clock Input. For normal operation, KILLRXCLK is

High. When this input is Low, it will force POCLK output to a logic

"0" state.

T1 Serial Clock Loop Time Select input. Active High. When High,

SLPTIME enables the recovered clock from the receive section to

be used in place of the synthesized transmit clock.

T2 Reference Clock Looptime Select input. Active High. When High,

RLPTIME enables POCLK from the receiver to be used as the

reference clock input to the transmitter.

P15 Master Reset. Reset input for the device, Active Low. During

Reset, all clocks are disabled.

N2 Test Enable. Used for production testing. Low for normal

operation.

R14 VCO ÷ by 16 Clock Output from the clock synthesizer. This output

T15 should be connected to the reference clock input of the external

clock recovery function (such as the S3066). It is recommended

to tie 155MCKP/N to VCC when not used.

P14 VCO ÷ by 128 Clock Output from the clock synthesizer. This

output should be connected to the reference clock input of the

external clock recovery function. It is recommended to tie 19MCK

to VCC when not used.

H1 Lock Detect. Active High. Goes active after the PLL has locked to

the clock provided on the REFCLK pins. LOCKDET is an

asynchronous output.

September 17, 2002/ Revision A

11

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