IDT7025S17GGI(2012) 查看數據表（PDF） - Integrated Device Technology

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IDT7025S17GGI
(Rev.:2012)

HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

A0 - A2

SEM

VALID ADDRESS

tAW

tWR

tEW

tSAA

tOH

VALID ADDRESS

tACE

DATA0

R/W

tDW

DATAIN VALID

tSOP

tAS

tWP

tDH

DATA OUT

VALID(2)

tSWRD

OE

Write Cycle

tSOP

Read Cycle

NOTE:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

tAOE

2683 drw 11

Timing Waveform of Semaphore Write Contention(1,3,4)

A0"A"-A2"A"

MATCH

SIDE(2) "A"

R/W"A"

SEM"A"

A0"B"-A2"B"

SIDE(2) "B"

R/W"B"

tSPS

MATCH

SEM"B"

2683 drw 12

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.

61.432

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