IDT7025S17GGI(2012) 查看數據表（PDF） - Integrated Device Technology

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IDT7025S17GGI
(Rev.:2012)

HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM

Truth Table II — Address BUSY

Arbitration

Inputs

Outputs

Military, Industrial and Commercial Temperature Ranges

CEL CER

A0L-A12L

A0R-A12R

BUSYL(1) BUSYR(1)

Function

X X NO MATCH

H

H

Normal

HX

MATCH

H

H

Normal

XH

MATCH

H

H

Normal

LL

MATCH

(2)

(2)

Write Inhibit(3)

NOTES:

2683 tbl 17

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7025

are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

Truth Table III — Example of Semaphore Procurement Sequence(1,2,3)

Functions

D0 - D15 Left

D0 - D15 Right

Status

No Action

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Right Port Writes "0" to Semaphore

0

1

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.

2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Truth Table.

2683 tbl 18

Functional Description

The IDT7025 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location

in memory. The IDT7025 has an automatic power down feature controlled

by CE. The CE controls on-chip power down circuitry that permits the

respective port to go into a standby mode when not selected (CE = VIH).

When a port is enabled, access to the entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 1FFE

(HEX), where a write is defined as the CER = R/WR= VIL per Truth Table

I. The left port clears the interrupt by an address location 1FFE access

when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port

interrupt flag (INTR) is asserted when the left port writes to memory location

1FFF (HEX) and to clear the interrupt flag (INTR), the right port must access

the memory location 1FFF, The message (16 bits) at 1FFE or 1FFF is

user-defined, since it is an addressable SRAM location. If the interrupt

function is not used, address locations 1FFE and 1FFF are not used as

mail boxes, but as part of the random access memory. Refer to Truth Table

I for the interrupt operation.

6.1482

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