IDT7025S17GGI(2012) 查看數據表（PDF） - Integrated Device Technology
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IDT7025S17GGI Datasheet PDF : 22 Pages
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IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS (2)
tAS (3)
tWR (4)
CE"A"
R/W"A"
INT"B"
ADDR"B"
CE"B"
tINS (3)
tAS (3)
tRC
INTERRUPT CLEAR ADDRESS (2)
2683 drw 17
OE"B"
INT"B"
tINR(3)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2683 drw 18
Truth Tables
Truth Table I — Interrupt Flag(1)
R/WL
Left Port
CEL
OEL
A0L-A12L
INTL
R/WR
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
X
X
X
L(3)
L
X
L
L
1FFE
H(2)
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
Right Port
CER
OER
A0R-A12R
X
X
X
L
L
1FFF
L
X
1FFE
X
X
X
INTR
Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
2689 tbl 16
61.472
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