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LTC1164-6(Rev0) 查看數據表(PDF) - Linear Technology

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LTC1164-6 Datasheet PDF : 12 Pages
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LTC1164-6
TYPICAL PERFOR A CE CHARACTERISTICS
THD + Noise vs RMS Input
(Elliptic Response)
– 40
– 45
(fCLK/fC) = 100:1 OR 50:1
fIN = 1kHz, TA = 25°C
– 50
– 55
– 60
VS = ±5V
– 65
– 70
– 75
– 80
VS = ±7.5V
– 85
– 90
0.1
1
INPUT (VRMS)
5
1164-6 G17
THD + Noise vs RMS Input for
Single 5V (Elliptic Response)
– 40
– 45
(fCLK/fC) = 100:1 OR 50:1
fIN = 1kHz, TA = 25°C
– 50
– 55
AB
– 60
– 65
– 70
– 75
– 80
– 85
A. GND = 2.5V
B. GND = 2V
– 90
0.1
INPUT (VRMS)
1
2
1164-6 G18
Power Supply Current vs Power
Supply Voltage
12
11
– 55°C
10
9
8
25°C
7
125°C
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10
POWER SUPPLY (V+ OR V)
1164-6 G19
Transient Response
Transient Response
1ms/DIV
1164-6 G20
VS = ±7.5V, VIN = ±3V 100Hz SQUARE WAVE
fCLK = 500kHz, (fCLK/fC) = 100:1, fCUTOFF = 5kHz
ELLIPTIC RESPONSE
1ms/DIV
1164-6 G21
VS = ±7.5V, VIN = ±3V 100Hz SQUARE WAVE
fCLK = 800kHz, (fCLK/fC) = 160:1, fCUTOFF = 5kHz
LINEAR PHASE RESPONSE
PI FU CTIO S (14-Lead Dual-In-Line Package)
Power Supply Pins (4, 12)
The V+ (pin 4) and the V (pin 12) should be bypassed with
a 0.1µF capacitor to an adequate analog ground. The
filter’s power supplies should be isolated from other
digital or high voltage analog supplies. A low noise linear
supply is recommended. Using a switching power supply
will lower the signal-to-noise ratio of the filter. The supply
during power-up should have a slew rate less than 1V/µs.
When V+ is applied before V and V could go above
ground, a signal diode must be used to clamp V . Figures
1 and 2 show typical connections for dual and single
supply operation.
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 1 shows the clock’s low and high
6

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