MPC5200VR400B 查看數據表（PDF） - Freescale Semiconductor

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MPC5200VR400B

SDRAM/DDR Memory Controller

Freescale Semiconductor 

1.3.4 Resets

The MPC5200B has three reset pins:

• PORRESET—Power on Reset

• HRESET—Hard Reset

• SRESET—Software Reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires

the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section. Table 14

specifies the pulse widths of the Reset inputs.

Table 14. Reset Pulse Width

Name

Description

Min Pulse Width

Max Pulse

Width

PORRESET Power On Reset tVDD_stable + tup_osc + tlock

—

HRESET Hardware Reset

4 clock cycles

—

SRESET

Software Reset

4 clock cycles

—

Reference Clock

SYS_XTAL_IN

SYS_XTAL_IN

SYS_XTAL_IN

SpecID

A3.1

A3.2

A3.3

For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards

its minimum pulse width equals the minimum given for HRESET related to the same reference clock.

The tVDD_stable describes the time which is needed to get all power supplies stable.

For tlock, refer to the Oscillator/PLL section of this specification for further details.

For tup_osc, refer to the Oscillator/PLL section of this specification for further details.

Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.

The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096

clock cycles.

NOTE

As long as VDD is not stable the HRESET output is not stable.

Table 15. Reset Rise/Fall Timing

Description

PORRESET fall time

PORRESET rise time

HRESET fall time

HRESET rise time

SRESET fall time

SRESET rise time

Min

Max

Unit

SpecID

—

1

ms

A3.4

—

1

ms

A3.5

—

1

ms

A3.6

—

1

ms

A3.7

—

1

ms

A3.8

—

1

ms

A3.9

NOTE

Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter

to prevent them from getting into the chip. HRESET and SRESET must have a monotonous

rise time. The assertion of HRESET becomes active at Power on Reset without any

SYS_XTAL clock.

MPC5200B Data Sheet, Rev. 4

14

Freescale Semiconductor

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