MPC5200VR400B 查看數據表（PDF） - Freescale Semiconductor

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MPC5200VR400B

SDRAM/DDR Memory Controller

Freescale Semiconductor 

MEM_CLK

Control Signals

DQM (Data Mask)

MDQ (Data)

MA (Address)

MBA (Bank Selects)

tvalid

thold

Active

NOP WRITE

NOP

DMvalid

DMhold

NOP

datavalid

tvalid

tvalid

thold

Row

thold

datahold

Column

NOP

NOP

NOP

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing

1.3.6.3 Memory Interface Timing-DDR SDRAM Read Command

The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value

is calculated automatically by hardware.

Table 20. DDR SDRAM Memory Read Timing

Sym

tmem_clk

tvalid

thold

datasetup

datahold

Description

MEM_CLK period

Control Signals, Address and MBA

valid after rising edge of MEM_CLK

Control Signals, Address and MBA

hold after rising edge of MEM_CLK

Setup time relative to MDQS

Hold time relative to MDQS

Min

7.5

—

tmem_clk × 0.5

—

2.6

Max

—

tmem_clk × 0.5 + 0.4

Units SpecID

ns A5.15

ns A5.16

—

ns A5.17

0.4

ns A5.18

—

ns A5.19

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

19

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