MPC5200B 查看數據表（PDF） - Freescale Semiconductor

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MPC5200B

SDRAM/DDR Memory Controller

Freescale Semiconductor 

2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt

sources. Take care of interrupt prioritization which may increase the latencies.

Because all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has

to exceed a minimum pulse width of more than one IP_CLK cycle.

Table 17. Minimum Pulse Width for External Interrupts to be Recognized

Name

All external interrupts (IRQs, GPIOs)

Min Pulse Width

> 1 clock cycle

Max Pulse Width

—

Reference Clock SpecID

IP_CLK

A4.22

NOTES:

1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200B User’s Manual

(MPC5200BUM) for further information.

2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second

interrupt is not recognized at all.

Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt

service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended

to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design

and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.

1.3.6 SDRAM

1.3.6.1 Memory Interface Timing-Standard SDRAM Read Command

Table 18. Standard SDRAM Memory Read Timing

Sym

Description

Min

Max

Units SpecID

tmem_clk

MEM_CLK period

7.5

tvalid Control Signals, Address and MBA Valid after

—

rising edge of MEM_CLK

—

ns

tmem_clk × 0.5 + 0.4 ns

thold Control Signals, Address and MBA Hold after tmem_clk × 0.5

rising edge of MEM_CLK

—

ns

DMvalid DQM valid after rising edge of MEM_CLK

—

tmem_clk × 0.25 + 0.4 ns

DMhold DQM hold after rising edge of MEM_CLK tmem_clk × 0.25 – 0.7

—

ns

datasetup MDQ setup to rising edge of MEM_CLK

—

0.3

ns

datahold MDQ hold after rising edge of MEM_CLK

0.2

—

ns

A5.1

A5.2

A5.3

A5.4

A5.5

A5.6

A5.7

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

17

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