MAX6876 查看數據表（PDF） - Maxim Integrated
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MAX6876 Datasheet PDF : 39 Pages
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EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
catch up. When the slave’s voltages approach the ramp
voltage, the slave releases HOLD and the master allows
the ramp voltage to begin rising again. All tracking must
be completed by the selected tracking fault timeout peri-
od or the supplies are powered down. The slave HOLD
output is asserted low until the selected tracking IN_ volt-
ages are within their selected thresholds. This ensures
that the master does not begin the tracking operation until
the slave’s input voltages (IN_) have properly stabilized.
Sequencing
The sequencing operation can be initialized by proper-
ly setting the bit of registers 0Bh and 0Ch. During a
sequencing power-up phase, each OUT_ is indepen-
dently powered on with a controlled slew rate. No more
than one supply is powered on for each generated
ramp. The bits of registers 0Bh and 0Ch establish the
turn-on order. During each phase, the ramp is enabled
to start only after the tGATE timeout has been counted.
The sequencing phase will be considered complete
when all the channels programmed to power on reach
the independently set PG_ thresholds (see Figure 5).
Mixed Mode (Tracking/Sequencing)
The MAX6876 is fully programmable to generate up to
four ramps during power-up or power-down modes.
Each OUT_ voltage independently is programmed to
follow any of the control ramps generated by the
MAX6876. To do the latter, set the bits on register 0Bh
and 0Ch to “1” for each channel. The following are pro-
gramming examples of different power-up modes (© =
sequence, / = track):
0Bh = 0000 1111 0Ch = 0000 0000 tracking mode:
OUT1/OUT2/OUT3/OUT4 on Ramp1
0Bh = 1000 0100 0Ch = 0010 0001 sequencing
mode: OUT3 © OUT4 © OUT1 © OUT2 on Ramp1,
Ramp2, Ramp3, Ramp4
0Bh = 1100 0001 0Ch = 0010 0000 mix mode*: OUT1
© OUT4/OUT3 © OUT2 on Ramp1, Ramp2, Ramp4
*(Ramp3 is not considered because no OUT_ outputs
are selected by bit [0:3] of 0Ch.)
Drive ENABLE or TRKEN low or use a software com-
mand to initiate a controlled power-down. The MAX6876
powers down the OUT_ voltages in a reverse sequence
from the one at power-up when this option is selected.
For example, with the following power-up sequence:
OUT1 © OUT4/OUT3 © OUT2
then the power-down sequence will be:
OUT2 © OUT4/OUT3 © OUT1
Configuring Tracking and Sequencing
Modes
To configure tracking and sequencing modes, insert
“1” and “0” into the 0Bh and 0Ch registers (see Table
2). Figure 6 shows how to map for tracking and
sequencing modes. Each OUT_ output can follow one
of the four possible ramps in tracking or sequencing
mode (16 bits are available) and one bit set to “1,”
means that the channel of the interested row is pow-
ered up/down by the corresponding ramp (see Figure
6).
1) If the depicted table (in Figure 6) is made by all “1s,”
the part simply generates a single ramp (all channels
in tracking mode since the first column is full of “1s,”)
and it ignores the remaining values of the other 12 bits.
2) If one row contains more than one symbol “1,” only
the first encountered (columns starting with R0Bh
[3:0]) is taken into account and the channel is pow-
ered up/down with the corresponding ramp.
3) If there is one (or more) row in which all 4 bits are
set to “0,” it means that the device will not control
that particular channel.
4) If there is one (or more) column where all 4 bits are
set to “0,” the device skips that ramp and its associ-
ate tD-GATE.
In master-slave applications, the device is intended to
provide only tracking for the four supplies (only one
ramp can be generated). To control one particular
channel, only insert a “1” in any of the four possible
positions (one row for each channel contains 4 bits)
and the device generates the proper signals. When
three or less ramps are needed, use consecutive
ramps starting with ramp 1.
Power-Down and Power-Up
When all the IN_ inputs are within the selected threshold
range and the internal enable is logic high (Figure 7), the
device initiates a power-up phase. During power-up, the
OUT_ outputs are forced by an internal loop that controls
the GATE_ of the external MOSFET to follow the reference
ramp voltage. This phase for each individual ramp must
be completed within the programmable fault timeout time;
otherwise, the part will force a shutdown on the GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing the internal enable low. Two
power-down options are available: a fast-shutdown option
where all GATE_ gates are quickly turned off or a reverse-
order option. This reverse-order option allows the OUT_
voltage to be powered down with a controlled slew rate
and in the reverse order they have been powered up (see
Figure 2).
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