25P10AV 查看數據表（PDF） - STMicroelectronics

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25P10AV

1 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface

STMicroelectronics 

M25P10-A

4

Operating features

Operating features

4.1

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one

byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is

followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)

and Table 16: Instruction Times (Device Grade 6)).

4.2

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the

entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of

duration tSE or tBE).

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

4.3

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase

(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The

Write In Progress (WIP) bit is provided in the Status Register so that the application program

can monitor its value, polling it to establish when the previous Write cycle, Program cycle or

Erase cycle is complete.

4.4

Active Power, Standby Power and Deep Power-Down Modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

When Chip Select (S) is High, the device is deselected, but could remain in the Active Power

mode until all internal cycles have completed (Program, Erase, Write Status Register). The

device then goes in to the Standby Power mode. The device consumption drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Deep Power-

down (DP) instruction) is executed. The device consumption drops further to ICC2. The

device remains in this mode until another specific instruction (the Release from Deep

Power-down and Read Electronic Signature (RES) instruction) is executed.

While in the Deep Power-down mode, the device ignores all Write, Program and Erase

instructions (see Deep Power-down (DP)). This can be used as an extra software protection

mechanism, when the device is not in active use, to protect the device from inadvertent

Write, Program or Erase instructions.

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