AD9633 查看數據表（PDF） - Analog Devices
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AD9633 Datasheet PDF : 42 Pages
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AD9633
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Input Clock Rate
Conversion Rate4
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)5
DCO to Data Delay (tDATA)5
DCO to FCO Delay (tFRAME)5
Lane Delay (tLD)
Data to Data Skew (tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)6
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
10
10
1.5
1.5
(tSAMPLE/12) − 300
(tSAMPLE/12) − 300
Typ
Max
6.25/4.76/4.00
6.25/4.76/4.00
1000
80/105/125
2.3
300
300
2.3
tFCO + (tSAMPLE/12)
(tSAMPLE/12)
(tSAMPLE/12)
90
±50
250
375
16
3.1
3.1
(tSAMPLE/12) + 300
(tSAMPLE/12) + 300
±200
1
135
1
Unit
MHz
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ps
ns
μs
Clock cycles
ns
fs rms
Clock cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output
mode.
5 tSAMPLE/12 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.
6 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. B | Page 6 of 41
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