AD9633 查看數據表（PDF） - Analog Devices
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AD9633 Datasheet PDF : 42 Pages
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Data Sheet
AD9633
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 73
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 73)
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 73)
Limit Unit
1.2
ns min
−0.2 ns min
2
ns min
2
ns min
40
ns min
2
ns min
2
ns min
10
ns min
10
ns min
10
ns min
10
ns min
Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 21 for SPI register settings.
VIN±x
N–1
tA
N
N+1
CLK–
CLK+
DDR
SDR
DCO+
DCO–
DCO+
DCO–
FCO–
BITWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
FCO–
BYTEWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
tEH
tEL
tCPD
tFCO
tFRAME
tPD
tDATA
D10 D08 D06 D04 D02 LSB D10 D08 D06 D04 D02 LSB
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
tLD
MSB D09 D07 D05 D03 D01 MSB D09 D07 D05 D03 D01
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16
Figure 2. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)
Rev. B | Page 7 of 41
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