74LVC109D,118 查看數據表（PDF） - NXP Semiconductors.
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74LVC109D,118 Datasheet PDF : 18 Pages
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Philips Semiconductors
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
74LVC109
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
SYMBOL
PARAMETER
Tamb = −40 to 85 °C; note 1
tPHL/tPLH propagation delay nCP to nQ and
nCP to nQ
tPLH
propagation delay nSD to nQ and
nRD to nQ
tPHL
propagation delay nSD to nQ and
nRD to nQ
tW
trem
tsu
th
fmax
tsk(0)
clock pulse width HIGH or LOW
set or reset pulse width HIGH or
LOW
removal time nSD, nRD to nCP
set-up time nJ and nK to CP
hold time nJ and nK to nCP
maximum clock pulse frequency
skew
TEST CONDITIONS
WAVEFORMS VCC (V)
see Figs 6 and 8 1.2
2.7
3.0 to 3.6
see Figs 7 and 8 1.2
2.7
3.0 to 3.6
see Figs 7 and 8 1.2
2.7
3.0 to 3.6
see Fig. 6
3.0 to 3.6
see Fig. 7
3.0 to 3.6
see Fig. 7
see Fig. 6
see Fig. 6
see Fig. 6
note 3
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
MIN.
−
1.5
1.0
−
1.5
1.0
−
1.5
1.0
3.3
3.0
3.0
2.5
2.0
150
−
TYP.
15
2.8
3.8(2)
16
4.0
3.2(2)
13
4.7
3.5(2)
2.0
−
−
−
−
330
−
MAX. UNIT
−
ns
7.3
ns
6.8
ns
−
ns
8.2
ns
7.0
ns
−
ns
7.1
ns
6.5
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
MHz
1.0
ns
2004 Mar 18
9
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