EN80960SA 查看數據表（PDF） - Intel

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EN80960SA

EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS

Intel 

80960SA

HIGH LEVEL (MIN) 0.7VCC

T1

T3

90%

1.5 V

LOW LEVEL (MAX) 0.8V

10%

T5

T4

T2

Figure 12. Processor Clock Pulse (CLK2)

CLK2

CLK

ABC DABC

OUTPUTS

RESET

INT0, INT1,

INT3, LOCK

T17

T16

T15

INITIALIZATION PARAMETERS

NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 “A” edge.

Figure 13. RESET Signal Timing

19

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