LPC1817JBD144 查看數據表（PDF） - NXP Semiconductors.

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LPC1817JBD144

32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC

NXP Semiconductors. 

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB

SRAM; Ethernet, two High-speed USB, LCD, EMC

Rev. 5.2 — 8 March 2016

Product data sheet

1. General description

The LPC185x/3x/2x/1x are ARM Cortex-M3 based microcontrollers for embedded

applications. The ARM Cortex-M3 is a next generation core that offers system

enhancements such as low power consumption, enhanced debug features, and a high

level of support block integration.

The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The LPC185x/3x/2x/1x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of

EEPROM memory, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM

(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external

memory controller, and multiple digital and analog peripherals.

For additional documentation related to the LPC18xx parts, see Section 17 “References”.

2. Features and benefits

 Processor core

 ARM Cortex-M3 processor (version r2p1), running at CPU frequencies of up to

180 MHz.

 ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 On-chip memory

 Up to 1 MB on-chip dual bank flash memory with flash accelerator.

 16 kB on-chip EEPROM data memory.

 136 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access.

 64 kB ROM containing boot code and on-chip software drivers.

 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose

use.

 Clock generation unit

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