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LPC1817JBD144 查看數據表(PDF) - NXP Semiconductors.

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LPC1817JBD144 Datasheet PDF : 155 Pages
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NXP Semiconductors
LPC185x/3x/2x/1x
32-bit ARM Cortex-M3 microcontroller
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
Four general-purpose timer/counters with capture and match capabilities.
One motor control PWM for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer.
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
Event recorder with three inputs to record event identification and event time; can
be battery powered.
Alarm timer; can be battery powered.
Analog peripherals:
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight analog channels total. Each analog input is connected to both ADCs.
Unique ID for each device.
Power:
Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip internal voltage regulator for
the core supply and the RTC power domain.
RTC power domain can be powered separately by a 3 V battery supply.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
Brownout detect with four separate thresholds for interrupt and forced reset.
Power-On Reset (POR).
Available in LQFP208, LBGA256, LQFP144, and TFBGA100 packages.
3. Applications
Industrial
Consumer
White goods
RFID readers
e-Metering
LPC185X_3X_2X_1X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.2 — 8 March 2016
© NXP B.V. 2016. All rights reserved.
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