LPC1817JBD144 查看數據表（PDF） - NXP Semiconductors.

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LPC1817JBD144

32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC

NXP Semiconductors. 

NXP Semiconductors

LPC185x/3x/2x/1x

32-bit ARM Cortex-M3 microcontroller

0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are

tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are

eight ADC channels total for the two ADCs.

Table 3. Pin description

Pin name

Description

Multiplexed digital pins

P0_0

L3 G2 32 47 [2] N; I/O GPIO0[0] — General purpose digital input/output pin.

PU I/O SSP1_MISO — Master In Slave Out for SSP1.

I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

- R — Function reserved.

- R — Function reserved.

- R — Function reserved.

I/O I2S0_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

I/O I2S1_TX_WS — Transmit Word Select. It is driven by the

master and received by the slave. Corresponds to the signal

WS in the I2S-bus specification.

P0_1

M2 G1 34 50 [2] N; I/O GPIO0[1] — General purpose digital input/output pin.

PU I/O SSP1_MOSI — Master Out Slave in for SSP1.

I ENET_COL — Ethernet Collision detect (MII interface).

- R — Function reserved.

- R — Function reserved.

- R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII

interface).

I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the

transmitter and read by the receiver. Corresponds to the signal

SD in the I2S-bus specification.

P1_0

P2 H1 38 54 [2] N; I/O GPIO0[4] — General purpose digital input/output pin.

PU I CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.

I/O EMC_A5 — External memory address line 5.

- R — Function reserved.

- R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

- R — Function reserved.

I/O EMC_D12 — External memory data line 12.

LPC185X_3X_2X_1X

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5.2 — 8 March 2016

© NXP B.V. 2016. All rights reserved.

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