GBE-PCS-PM-U1 查看數據表（PDF） - Lattice Semiconductor

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GBE-PCS-PM-U1

Gigabit Ethernet PCS IP Core for LatticeECP2M

Lattice Semiconductor 

Lattice Semiconductor

Gigabit Ethernet PCS IP Core

for LatticeECP2M

Core Generation

The GbE PCS IP core is available for download from the Lattice website at www.latticesemi.com. The IP files are

automatically installed using ispUPDATE technology in any directory of your choosing.

The ispLEVER IPexpress GUI window for the GbE PCS IP core is shown in Figure 6. To generate a specific IP core

configuration you must specify:

• Project Path – Path to directory where the generated IP files will be loaded.

• File Name – “username” designation given to the generated IP core and corresponding folders and files.

• Design Entry type – Verilog HDL.

• Device Family – Device family to which IP is to be targeted. Only families that support the particular core are

listed.

• Part Name – Specific targeted part within the selected Device Family.

Note that if IPexpress is called from within an existing project, Project Path, Design Entry, Device Family and Part

Name default to the specified project parameters. Please refer to the IPexpress on-line help for further information.

Figure 6. IPexpress Dialog Box

To create a custom configuration, click on the Customize button to display the GbE PCS IP core Configuration

GUI, shown in Figure 7. From this window you may start the core generation process.

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