GBE-PCS-PM-U1 查看數據表（PDF） - Lattice Semiconductor

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GBE-PCS-PM-U1

Gigabit Ethernet PCS IP Core for LatticeECP2M

Lattice Semiconductor 

Lattice Semiconductor

Gigabit Ethernet PCS IP Core

for LatticeECP2M

These are all of the files that you need to implement and verify the GbE PCS IP core in your own top-level design.

The following additional files providing IP core generation status information are also generated in the “Project

Path” directory:

• <username>_generate.log – ispLEVER synthesis and map log file

• <username>_gen.log – IPexpress IP generation log file

The \<gbe_pcs_eval> and subtending directories provide files supporting GbE PCS core evaluation. The

\<gbe_pcs_eval> directory contains files/folders with content that is constant for all configurations of the GbE

PCS. The \<username> subfolder (\gbepcs_core0 in this example) contains files/folders with content specific

to the username configuration.

The \gbe_pcs_eval directory is created by IPexpress the first time the core is generated and updated each time

the core is regenerated. A \<username> directory is created by IPexpress each time the core is generated and

regenerated each time the core with the same file name is regenerated. A separate \<username> directory is

generated for cores with different names, e.g. \<gbepcs_core1>, \<gbepcs_core2>, etc.

Instantiating the Core

The generated GbE PCS IP core package includes black-box (<username>_bb.v) and instance (<user-

name>_inst.v) templates that can be used to instantiate the core in a top-level design. Two example RTL top-

level source files are provided in \<project_dir>\gbe_pcs_eval\<username>\src\rtl\top\<technol-

ogy>.

The top-level file top.v is a GbE Physical Layer Reference design (described in Appendix B). Additional files asso-

ciated with the reference design are located in the directory \<project_dir>\gbe_pcs_eval\<user-

name>\src\rtl\template\<technology>.

The top-level file top_gbe_pcs_core_only.v supports the ability to implement just the GbE PCS core by itself.

This design is intended only to provide an indication of the device utilization associated with the GbE PCS IP core

and should not be used as an actual implementation example.

Running Functional Simulation

The functional simulation model generated in the “Project Path” root directory (<username>_beh.v) may be

instantiated in the your testbench for evaluation in the context of your application. Lattice does not provide a test-

bench for evaluating this IP core in isolation. However, a function simulation capability is provided in which <user-

name>_beh.v is instantiated in an FPGA top level that implements a complete GbE Physical Layer as discussed

previously and described in an appendix to this document. The top-level file supporting ModelSim® simulation is

provided in \<project_dir>\gbe_pc_eval\<username>\sim\modelsim. This FPGA top is instantiated in

an eval testbench provided in \<project_dir>\gbe_psc_eval\testbench.

You may run the eval simulation by doing the following:

1. Open ModelSim.

2. Under the File tab, select Change Directory and choose folder:

<project_dir>\gbe_pcs_eval\<username>\sim\modelsim.

3. Under the Tools tab, select TCL _ Execute Macro and execute the ModelSim “do” script shown.

The simulation waveform results will be displayed in the ModelSim Wave window.

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