T2080 查看數據表（PDF） - Freescale Semiconductor

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T2080

T2080 Product Brief Also supports T2081

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• Traditional routing and bridging

• Firewall

• Security protocol encapsulation and encryption

The functions off-loaded by the DPAA fall into two broad categories:

• Packet distribution and queue-congestion management

• Accelerating content processing

Chip features

4.10.1 DPAA terms and definitions

The QorIQ Platform's Data Path Acceleration Architecture (henceforth DPAA) assumes the existence of network flows,

where a flow is defined as a series of network datagrams, which have the same processing and ordering requirements. The

DPAA prescribes data structures to be initialized for each flow. These data structures define how the datagrams associated

with that flow move through the DPAA. Software is provided a consistent interface (the software portal) for interacting with

hardware accelerators and network interfaces.

All DPAA entities produce data onto frame queues (a process called enqueuing) and consume data from frame queues

(dequeuing). Software enqueues and dequeues through a software portal (each vCPU has two software portals), and the

FMan, RMan, and DPAA accelerators enqueue/dequeue through hardware portals. This figure illustrates this key DPAA

concept.

This table lists common DPAA terms and their definitions.

Table 3. DPAA terms and definitions

Term

Buffer

Definition

Region of contiguous memory, allocated by software, managed

by the DPAA BMan

Graphic representation

Buffer pool Set of buffers with common characteristics (mainly size,

alignment, access control)

Frame

Single buffer or list of buffers that hold data, for example, packet

payload, header, and other control information

Frame queue FIFO of frames

(FQ)

Work queue FIFO of FQs

(WQ)

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T2080 Product Brief, Rev 0, 04/2014

Freescale Semiconductor, Inc.

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