NT68625MEFG-128 查看數據表（PDF） - Novatek Microelectronics

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NT68625MEFG-128

Flat Panel Monitor Controller

Novatek Microelectronics 

53 DVDD

54 RSBA1P/

V0

55 RSBA1M/

V1

56 RSBA2P/

V2

57 RSBA2M/

V3

58 RSBA3P/

V4

59 RSBA3M/

V5

60 RSCLKAP/

V6

61 RSCLKAM/

V7

62 RSGA1P/

YUV_CLK

63 RSGA1M

64 DGND/CGND

65 PA0

PWM2

66 PA2

PWM4

67 PA1

PWM3

68 RSGA2P/T7P

69 RSGA2M/T7M

70 RSGA3P/TCLK2P

71 RSGA3M/TCLK2M

72 RSRA1P/T6P/

RSBB0P

73 RSRA1M/T6M/

RSBB0M

74 RSRA2P/T5P/

RSGB0P

75 RSRA2M/T5M/

RSGB0M

76 RSRA3P/T4P/

RSRB0P

77 RSRA3M/T4M/

RSRB0M

78 DGND/CGND

NT68665/NT68625

(0.1uF) connected is recommended.

Power Display Digital Power Supply

RSDSO Port A Blue data RSDS differential data 1 (Positive)/

Video data input

RSDSO Port A Blue data RSDS differential data 1 (Negative)/

Video data input

RSDSO Port A Blue data RSDS differential data 2 (Positive) /

Video data input

RSDSO Port A Blue data RSDS differential data 2 (Negative)/

Video data input

RSDSO Port A Blue data RSDS differential data 3 (Positive) /

Video data input

RSDSO Port A Blue data RSDS differential data 3 (Negative)/

Video data input

RSDSO Port A Pixel clock RSDS differential positive/

Video data input

RSDSO Port A Pixel clock RSDS differential Negative

/Video data input

RSDSO Port A Green data RSDS differential data 1 (Positive)

/Video Port Clock

RSDSO Port A Green data RSDS differential data 1 (Negative)

Power Digital Ground/ Core Logic Ground

I/O

I/O Pin; Schmitt Trigger Input

O

PWM-Type D/A Converter; 3.3V Push-Pull Structure

I/O

I/O Pin; Schmitt Trigger Input

O

PWM-Type D/A Converter; 3.3V Push-Pull Structure

I/O

I/O Pin; Schmitt Trigger Input

O

PWM-Type D/A Converter; 3.3V Push-Pull Structure

RSDSO/ Port A Green data RSDS differential data 2 (Positive)/

LVDSO/ Positive LVDS differential data output of channel 7/

RSDSO/ Port A Green data RSDS differential data 2 (Negative)/

LVDSO/ Negative LVDS differential data output of channel 7

RSDSO/ Port A Green data RSDS differential data 3 (Positive)/

LVDSO/ Positive LVDS differential clock 2 output

RSDSO/ Port A Green data RSDS differential data 3 (Negative)/

LVDSO/ Negative LVDS differential clock 2 output

RSDSO/ Port A Red data RSDS differential data 1 (Positive)/

LVDSO/ Positive LVDS differential data output of channel 6

RSDSO/ Port A Red data RSDS differential data 1 (Negative)/

LVDSO/ Negative LVDS differential data output of channel 6

RSDSO/ Port A Red data RSDS differential data 2 (Positive)/

LVDSO/ Positive LVDS differential data output of channel 5

RSDSO/ Port A Red data RSDS differential data 2 (Negative)/

LVDSO/ Negative LVDS differential data output of channel 5

RSDSO/ Port A Red data RSDS differential data 3 (Positive)/

LVDSO/ Positive LVDS differential data output of channel 4

RSDSO/ Port A Red data RSDS differential data 3 (Negative)/

LVDSO/ Negative LVDS differential data output of channel 4

Power Digital Ground/ Core Logic Ground

2006-02-09

13

Ver. 0.40

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