NT68625MEFG-128 查看數據表（PDF） - Novatek Microelectronics
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NT68625MEFG-128 Datasheet PDF : 185 Pages
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114 INT_HSO/GPO5
115 CVDD
116 GPO6
117 PWMA/GPO7
118 PWMB/GPO8
119 NC
120 PC0*
121 PC1*
122 PC3
PWM0
123 PC4
PWM1
124 PC5
125 PB1/ADC1
126 PB0/ADC0
127 OSCO
128 OSCI
O
Power
O
O
O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
I/O
I/O
O
I
NT68665/NT68625
Internal Horizontal Sync output, this signal is by-pass the
Sync-processor / General purpose output
Core logic power supply (1.8V) pin. External capacitor
(0.1uF) connected is recommended.
General purpose output
PWMA/ General purpose output
PWMB/ General purpose output
MCU VSYNCI test pin
I/O Pin; 5V Open-Drain Structure with Schmitt Trigger
Input
I/O Pin; 5V Open-Drain Structure with Schmitt Trigger
Input
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
PWM-Type D/A Converter; Push-Pull Structure
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
PWM-Type D/A Converter; Push-Pull Structure
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
A/D Converter Input-1; Hi-Z input
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
A/D Converter Input-0; Hi-Z input
12MHz External Crystal OSC Output
12MHz External Crystal OSC Input
Table 5.2-1 Pin List
5.3. Pin Description
System Interface
Pin
Type Pin No. Drive Definition
TCLK
IRQn
RSTn
SDA
SCL
I
44
O
51
I (5V 48
tolerant)
I (5V 49
tolerant)
I/O 48
(5V
tolerant)
Reference clock Input
4 mA Interrupt Request
System Reset
Host Interface Serial Data In/Out.
Host Interface Serial Clock.
Graphic Analog Interface
Pin
Type Pin No.
ADC_GNDA
ADC_VAA
BIN1+
BIN1-
SOGI1
GIN1+
Power 27
Power 26
I
19
I
20
I
21
I
22
Drive
Definition
B channel ADC analog ground
B channel ADC analog power supply
B channel positive analog video input
B channel negative analog video input
VGA Port 1 Sync On Green Input with Schmitt trigger
G channel positive analog video input
2006-02-09
15
Ver. 0.40
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