NT68625MEFG-128 查看數據表（PDF） - Novatek Microelectronics
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NT68625MEFG-128 Datasheet PDF : 185 Pages
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NT68665/NT68625
6. Functional Description
6.1. Power Control
NT68665/NT68625 supports the whole chip power down function. By setting the CHIP_PWDN bit to
‘1’, NT68665/NT68625 will go into power down state except the I2C logic and Sync-processor
(include SOG Slicer, and TMDS Sync Detect) will keep alive.
GI_SRC_SEL
WARM_RST
GI_TMDS
PD
VI_YUV
PD
DISP
PD
GI_ADC
PD
Scaling
PD
TC
(optional)
PD
TMDS
EN
ADC
EN
ADPLL
EN
HPLL
EN
PU_TMDS
PU_ADC
PU_PLL
LVDS
(optional)
PD
PU_HPLL
(hpll_en)
PU_LVDS
Power Control Block
Figure 6.1-1 Power Control Block
DPLL/SSC
EN
PU_DDDS
(dds_en)
6.2. Analog to Digital Converter (ADC)
NT68665/NT68625 provides a clock-recovery circuit and an analog-to-digital converter to effectively
save the cost of needing external expensive ADC and PLL. The gain and offset circuit is used to
adjust the gain (Contrast) of input video amplitude and shift the DC offset voltage (Brightness). The
clock-recovery circuit consisting of a high-speed phase lock loop (PLL) is used to generate the clock
to sample analog RGB data. This circuit is locked to the HSYNC of the incoming video signal. The
analog-to-digital converter (ADC) transfers the input analog RGB video to digital output data with each
color 8-bit resolution.
Gain and Offset Control
RIN/GIN/BIN are high-impedance input pins that accept the RED, GREEN, and BLUE channel
graphics signals. They accommodate input signals ranging from 0.55V to 0.9V full scale. Signals
should be AC-couple to these pins.
Due to AC coupling, clamping pulse is needed to define the time during which the input signal is
clamped to ground, establishing a black reference. Typically the clamping pulse is defined during the
back porch period of the graphics signal. NT68665/NT68625 generates the clamping pulse internally
2006-02-09
19
Ver. 0.40
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