ADDS-21160M-EZLITE 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADDS-21160M-EZLITE

1 MSPS 16-/14-Bit Analog I/O Port

Analog Devices 

AD15700

Decoding Multiple DACs

The CS_DAC pin of the DAC can be used to select one of a

number of DACs. All devices receive the same serial clock and

serial data, but only one device will receive the CS_DAC signal

at any one time. The DAC addressed will be determined by the

decoder. There will be some digital feedthrough from the digital

input lines. Using a burst clock will minimize the effects of digital

feedthrough on the analog signal channels. Figure 38 shows a

typical circuit.

SCLK

DIN

VDD

DAC

CS_DAC

DIN

VOUT

SCLK

ENABLE

CODED

ADDRESS

EN

DECODER

DGND

DAC

CS_DAC

DIN

VOUT

SCLK

DAC

CS_DAC

DIN

VOUT

SCLK

DAC

CS_DAC

DIN

VOUT

SCLK

Figure 38. Addressing Multiple DACs

AMPLIFIER THEORY OF OPERATION

The amplifiers are single and dual versions of high speed, low

power voltage feedback amplifiers featuring an innovative archi-

tecture that maximizes the dynamic range capability on the inputs

and outputs. Linear input common-mode range exceeds either

supply voltage by 200 mV, and the amplifiers show no phase

reversal up to 500 mV beyond supply. The output swings to

within 20 mV of either supply when driving a light load; 300 mV

when driving up to 5 mA.

The amplifier provides an impressive 80 MHz bandwidth when

used as a follower and 30 V/ms slew rate at only 800 mA supply

current. Careful design allows the amplifier to operate with a

supply voltage as low as 2.7 V.

Input Stage Operation

A simplified schematic of the input stage appears in Figure 39.

For common-mode voltages up to 1.1 V within the positive supply,

(0 V to 3.9 V on a single 5 V supply) tail current I2 flows through

the PNP differential pair, Q13 and Q17. Q5 is cut off; no bias

current is routed to the parallel NPN differential pair Q2 and Q3.

As the common-mode voltage is driven within 1.1 V of the positive

supply, Q5 turns on and routes the tail current away from the PNP

pair and to the NPN pair. During this transition region, the

amplifier’s input current will change magnitude and direction.

Reusing the same tail current ensures that the input stage has

the same transconductance (which determines the amplifier’s

gain and bandwidth) in both regions of operation.

Switching to the NPN pair as the common-mode voltage is

driven beyond 1 V within the positive supply allows the amplifier

to provide useful operation for signals at either end of the supply

voltage range and eliminates the possibility of phase reversal for

input signals up to 500 mV beyond either power supply. Offset

voltage will also change to reflect the offset of the input pair in

control. The transition region is small, on the order of 180 mV.

These sudden changes in the dc parameters of the input stage

can produce glitches that will adversely affect distortion.

Q9

1.1V

R5

50k⍀

VIN

Q5

VIP

? I2

90mA

R6

R7

850⍀ 850⍀

Q13

Q17

VCC

Q3

Q2

R8 R9

850⍀ 850⍀

R1

R2

2k⍀

? I3

25mA

2k⍀

Q6

1

Q8

4

Q10

1

Q7

4

? I4

25mA

Q14

4

1

Q15

Q11

4

1

Q16

OUTPUT STAGE,

COMMON-MODE

FEEDBACK

R3

R4

? I1

5mA

VEE

Q18

Q4

2k⍀

2k⍀

Figure 39. Simplified Schematic of Input Stage

REV. A

–39–

Share Link: