87C196LA 查看數據表（PDF） - Intel

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87C196LA

CHMOS 16-BIT MICROCONTROLLER

Intel 

87C196LA — AUTOMOTIVE

Name

PROG#

PVER

RD#

RESET#

RXD

SC1:0

SD1:0

Type

I

O

O

I/O

I/O

I/O

I/O

Table 4. Signal Descriptions (Continued)

Description

Programming Start

Duringprogramming, a falling edge latches data on the programming bus and

begins programming, while a rising edge ends programming. The current

location is programmed with the same data as long as PROG# remains

asserted, so the data on the programming bus must remain stable while

PROG# is active.

During a word dump, a falling edge causes the contents of an OTPROM

location to be output on the PBUS, while a rising edge ends the data transfer.

PROG# shares a package pin with P2.2 and EXTINT.

Program Verification

During slave or auto programming, PVER is updated after each programming

pulse. A high output signal indicates successful programming of a location,

while a low signal indicates a detected error.

PVER shares a package pin with P2.0 and TXD.

Read

Read-signal output to external memory. RD# is asserted only during external

memory reads.

RD# shares a package pin with P5.3.

Reset

A level-sensitive reset input to, and an open-drain system reset output from, the

microcontroller. Either a falling edge on RESET# or an internal reset turns on a

pull-down transistor connected to the RESET# pin for 16 state times. In the

powerdown and idle modes, asserting RESET# causes the chip to reset and

return to normal operating mode. After a device reset, the first instruction fetch

is from 2080H.

Receive Serial Data

In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it

functions as either an input or an open-drain output for data.

RXD shares a package pin with P2.1 and PALE#.

Clock Pins for SSIO0 and 1

For handshaking transfers, configure SC1:0 as open-drain outputs.

This pin carries a signal only during receptions and transmissions. When the

SSIO port is idle, the pin remains either high (with handshaking) or low (without

handshaking).

SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6.

Data Pins for SSIO0 and 1

These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure

SDx as a complementary output signal. For receptions, configure SDx as a

high-impedance input signal.

SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7.

12

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