87C196LA 查看數據表（PDF） - Intel
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87C196LA Datasheet PDF : 21 Pages
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87C196LA — AUTOMOTIVE
5.2 AC Characteristics (Over Specified Operating Conditions)
Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FXTAL1 = 8MHz with PLL
enabled in clock-doubler mode.
Table 7. AC Characteristics
Symbol
Parameter
Min
Max
Units
The 87C196LA will meet these specifications
FXTAL1
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
8.0
20.0
MHz(1)
4.0
10.0
f
Operating frequency, f = FXTAL1; PLL in 1x mode
8.0
Operating frequency, f = 2FXTAL1; PLL in 2x mode
20.0
MHz
t
Period t = 1/f
50
125
ns
TXHCH
XTAL1 High to CLKOUT High or Low
20
110
ns(2)
TCLCL
CLKOUT Cycle Time
2t
ns
TCHCL
CLKOUT High Period
t – 10
t + 15
ns
TCLLH
CLKOUT Falling to ALE Rising
– 10
15
ns
TLLCH
ALE Falling to CLKOUT Rising
– 20
15
ns
TLHLH
ALE Cycle Time
4t
ns
TLHLL
ALE High Period
t – 10
t + 10
ns
TAVLL
Address Setup to ALE Low
t – 15
ns
TLLAX
Address Hold after ALE Low
t – 40
ns
TLLRL
ALE Low to RD# Low
t – 30
ns
TRLCL
RD# Low to CLKOUT Low
4
30
ns
TRLRH
TRHLH
RD# Low to RD# High
RD# High to ALE Rising
t–5
t
t + 25
ns
ns(3)
TRLAZ
RD# Low to Address Float
5
ns
TLLWL
ALE Low to WR# Low
t – 10
ns
TCLWL
CLKOUT Low to WR# Falling Edge
–5
25
ns
TQVWH
Data Valid to WR# High
t – 23
ns
TCHWH CLKOUT High to WR# Rising Edge
– 10
15
ns
TWLWH WR# Low to WR# High
t – 20
ns
TWHQX Data Hold after WR# High
t – 25
ns
NOTES:
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only
down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
18
PRODUCT PREVIEW
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