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87C196LA 查看數據表(PDF) - Intel

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87C196LA Datasheet PDF : 21 Pages
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87C196LA — AUTOMOTIVE
Name
WRL#
XTAL1
XTAL2
Type
O
I
O
Table 4. Signal Descriptions (Continued)
Description
Write Low
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes to external memory. During 8-bit bus cycles, WRL# is
asserted for all write operations.
WRL# shares a package pin with P5.2, WR#, and PLLEN.
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR#
or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal
clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal.
When using an external clock source instead of the on-chip oscillator, connect
the clock input to XTAL1. The external clock signal must meet the VIH
specification for XTAL1.
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
14
PRODUCT PREVIEW

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