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AN754

Understanding Microchip’s CAN Module Bit Timing

Microchip Technology 

AN754

RESYNCHRONIZATION

Resynchronization is implemented to maintain the ini-

tial synchronization that was established by the hard

synchronization. Without resynchronization, the receiv-

ing nodes could get out of synchronization due to oscil-

lator drift between nodes.

Resynchronization is achieved by implementing a Dig-

ital Phase Lock Loop (DPLL) function which compares

the actual position of a recessive-to-dominant edge on

the bus to the position of the expected edge (within the

FIGURE 5: SYNCHRONIZING THE BIT TIME

Input Signal (e = 0)

SyncSeg) and adjusting the bit time as necessary.

The phase error of a bit is given by the position of the

edge in relation to the SyncSeg, measured in TQ, and

is defined as follows:

• e = 0; the edge lies within the SyncSeg.

• e > 0; the edge lies before the sample point. (TQ

added to PS1).

• e < 0; the edge lies after the sample point of the

previous bit. (TQ subtracted from PS2)

SyncSeg

PropSeg

SJW (PS1)

PhaseSeg1 (PS1)

Nominal Bit Time (NBT)

No Resynchronization (e = 0)

PhaseSeg2 (PS2)

SJW (PS2)

Sample

Point

Input Signal

(e > 0)

SyncSeg

PropSeg

SJW (PS1)

PhaseSeg1 (PS1)

Nominal Bit Time (NBT)

PhaseSeg2 (PS2)

SJW (PS2)

Sample

Point

Actual Bit Time

Resynchronization to a Slower Transmitter (e > 0)

Input Signal (e < 0)

SyncSeg

PropSeg

SJW (PS1)

PhaseSeg1 (PS1)

Nominal Bit Time (NBT)

PhaseSeg2 (PS2)

SJW (PS2)

Sample

Point

Actual Bit Time

Resynchronization to a Faster Transmitter (e < 0)

DS00754A-page 6

 2001 Microchip Technology Inc.

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