MAX17030GTL 查看數據表（PDF） - Maxim Integrated
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MAX17030GTL Datasheet PDF : 38 Pages
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1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description
PIN
NAME
FUNCTION
Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the
1
CSN3 negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive
2
CSP3
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the
output inductor is utilized for current sensing.
To disable phase 3, connect CSP3 to VCC and CSN3 to GND.
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC
3
THRM and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of
VCC) at the desired high temperature.
Current Monitor Output Pin. The output current at this pin is:
IIMON = GM(IMON) x V(CSP_,CSN_)
where GM(IMON) = 1.6mS typical and denotes summation over all enabled phases.
4
IMON
An external resistor RIMON between IMON and GNDS sets the current-monitor output voltage:
VIMON = ILOAD x RSENSE x GM(IMON) x RIMON
where RSENSE is the value of the effective current-sense resistance.
Choose RIMON such that VIMON does not exceed 900mV at the maximum expected load current IMAX.
IMON is high impedance when the MAX17030/MAX17036 are in shutdown.
Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are
precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The
5
ILIM
valley negative current-limit thresholds are typically -125% of the corresponding valley positive
current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of
22.5mV typ.
Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate:
Slew rate = (12.5mV/µs) x (71.5k/RTIME)
where RTIME is between 35.7k and 178k.
6
TIME
This “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes
and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is
always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions
is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew
rate defined above.
7
VCC
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target
voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator
(slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum
8
FB
of the inductor currents is essential for cycle-by-cycle stability.
The external connections and compensation at FB depend on the desired DC and transient (AC)
droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the
remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through
capacitor C, where the R x C time constant should be at least 3x the switching period per phase.
12 ______________________________________________________________________________________
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