AN383 查看數據表（PDF） - Silicon Laboratories
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AN383 Datasheet PDF : 69 Pages
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AN383
Figure 5 shows critical component layout with top and bottom side placement, top and bottom side routing, crystal
support, analog and digital input and output support, and support for all devices. For this reason it is referred to as
a universal layout. Either crystal or digital audio operation must be selected due to the multipurpose role of GPO3/
DCLK pin 17. Note that the RCLK trace is not a sensitive node when an external reference clock is used instead of
the crystal. For this reason, an external reference clock allows more routing flexibility. To support the crystal
oscillator feature, route the RCLK trace as far from the SDIO pin 8 and trace as possible by routing the RCLK trace
on the bottom layer.
F1, C14, C15, C18, R19 and R20 are placed as close to the chip as possible. For the Si4704/05/06/2x with the
short antenna option, pin 4 is populated with L1 and C4, C17 is not populated; for the Si473x AM receiver, C4 is
replaced with C16, L1 is replaced with L2, and C17 is populated.
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Figure 5. Layout Example 4
Place a ground plane under the Si47xx as shown in Figure 6, “Two Layer Stackup” or Figure 7, “Four Layer
Stackup”. For designs in which a continuous ground plane is not possible, place a local ground plane directly under
the Si47xx. Do not route signal traces on the ground layer under the Si47xx and do not route signal traces under
the Si47xx without a ground plane between the Si47xx and signal trace. Flood the primary and secondary layers
with ground and place stitching vias to create a low impedance connection between planes.
Do not route digital or RF traces over breaks in the ground plane. Route all traces to minimize inductive and
capacitive coupling by keeping digital traces away from analog and RF traces, minimizing trace length, minimizing
parallel trace runs, and keeping current loops small. In particular, care should be taken to avoid routing digital
signals or reference clock traces near or parallel to the VCO pins 1, 20 or LOUT/ROUT pins 14, 13. Digital traces
should be routed in between ground planes (on the inner layers) for best performance. If that is not possible, route
digital traces on the opposite side of the chip.
Route all GND (including RFGND) pins to the ground pad. The ground pad should be connected to the ground
plane using multiple vias to minimize ground potential differences. The exception is GND/RIN/DOUT when
designing for a universal layout.
Route power to the Si47xx by trace, ensuring that each trace is rated to handle the required current. Some trace
impedance is preferable so that the decoupling currents are forced to flow through decoupling caps C1, C2, and C3
directly to the ground pins and not by alternate pathways.
Place the Si47xx close to the antenna(s) to minimize antenna trace length and capacitance and to minimize
inductive and capacitive coupling. This recommendation must be followed for optimal device performance. Route
the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling.
Design, Place, and Route other circuits such that radiation in the band of interest is minimized.
Rev. 0.8
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