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AN383

Si47XX ANTENNA, SCHEMATIC, LAYOUT, AND DESIGN GUIDELINES

Silicon Laboratories 

AN383

LAYER 1 – PRIMARY

Figure 6. Two Layer Stackup

LAYER 2 – GROUND

LAYER 1 – PRIMARY

LAYER 2 – GROUND

Figure 7. Four Layer Stackup

LAYER 3 – ROUTE

LAYER 4 – SECONDARY

2.6. Si47xx 3x3 mm Design Checklist

The following design checklist summarizes the guidelines presented in this section:

 Place bypass caps C1, C2 and C3 as close as possible to the supply and ground pins.

 Place a via connecting C1, C2, and C3 to the power supplies such that the cap is between the Si47xx and the

via.

 Route a wide, low inductance return current path from the C1, C2, and C3 to the Si47xx GND pins.

 Route GND/LIN/DOUT pin 15 to the GND pad if designing only for the Si4702/03.

 Route C1 GND directly and only to GND pin 12. Do not connect GND via to C1.

 Place resistor R1 as close to pin GPO3/DCLK 17 as possible.

 Place R9 as close as possible to VA/LIN/DFS pin16 as possible.

 Place resistor R11 as close to pin VA/LIN/DFS 16 as possible.

 Place resistor R12 as close to pin GND/RIN/DOUT 15 as possible.

 Place the series termination resistors R2–R6, R13–R16 as close to the host controller as possible.

 Place caps C12 or C13 close to the chip if digital audio is used.

 Place the crystal X1 as close to GPO3/DCLK pin 17 and RCLK pin 9 as possible.

 Route the SDIO trace and RCLK trace as far away from each other as possible when using crystal X1.

 Place caps C10 and C11 such that they share a common GND connection.

 Place a ground plane under the device as shown in Figure 6, “Two Layer Stackup” or Figure 7, “Four Layer

Stackup”.

 Place a local ground plane directly under the device for designs in which a continuous ground plane is not

possible.

 Route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and

RF traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small.

 Route digital traces in between ground plane for best performance. If that is not possible, route digital traces on

the opposite side of the chip.

 Route all GND (including RFGND) pins to the ground pad. The ground pad should be connected to the ground

plane using multiple vias minimize ground potential differences. The exception is GND/RIN/DOUT when

designing for the universal layout.

 Route power to the Si47xx by trace, ensuring that each trace is rated to handle the required current.

 Do not route signal traces on the ground layer directly under the Si47xx.

 Do not route signal traces under the Si47xx without a ground plane between the Si47xx and signal trace.

 Do not route digital or RF traces over breaks in the ground plane.

 Do not route digital signals or reference clock traces near to the VCO pin 1 and 20 or the LOUT/ROUT output

pin 14 and 13.

16

Rev. 0.8

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