SST39VF1601C-70-4C-EQE(2010) 查看數據表（PDF） - Silicon Storage Technology

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SST39VF1601C-70-4C-EQE
(Rev.:2010)

16 Mbit (x16) Multi-Purpose Flash Plus

Silicon Storage Technology 

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Chip-Erase Operation

The SST39VF1601C/1602C provide a Chip-Erase opera-

tion, which allows the user to erase the entire memory

array to the ‘1’ state. This is useful when the entire device

must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or CE#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 7 for the command sequence, Figure 11 for tim-

ing diagram, and Figure 26 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored. When WP# is low, any attempt to Chip-Erase will

be ignored. During the command sequence, WP# should

be statically held high or low.

Write Operation Status Detection

The SST39VF1601C/1602C provide two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system write cycle time. The

software detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data# Poll-

ing or Toggle Bit read may be simultaneous with the

completion of the write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7 or DQ6. In order to pre-

vent spurious rejection, if an erroneous result occurs, the

software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

Data Sheet

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output sig-

nal. RY/BY# is an open drain output pin that indicates

whether an Erase or Program operation is in progress.

Since RY/BY# is an open drain output, it allows several

devices to be tied in parallel to VDD via an external pull-up

resistor. After the rising edge of the final WE# pulse in the

command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an

Erase or Program operation is in progress. When RY/BY#

is high (Ready), the devices may be read or left in standby

mode.

Data# Polling (DQ7)

When the SST39VF1601C/1602C are in the internal Pro-

gram operation, any attempt to read DQ7 will produce the

complement of the true data. Once the Program operation

is completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase oper-

ation, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the

rising edge of sixth WE# (or CE#) pulse. See Figure 9 for

Data# Polling timing diagram and Figure 23 for a flowchart.

©2010 Silicon Storage Technology, Inc.

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