ISL8201M 查看數據表（PDF） - Renesas Electronics
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ISL8201M Datasheet PDF : 16 Pages
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ISL8201M
3. Determine IPEAK for:
IPEAK IOUTMAX + ------2-I--L----
(EQ. 4)
where IL is the output inductor ripple current. In a high input
voltage, high output voltage application, such as 20V input to
5V output, the inductor ripple becomes excessive due to the
fixed internal inductor value. In such applications, the output
current will be limited from the rating to approximately 70% of
the module’s rated current.
The relationships between the external RSET values and the
typical output current IOUT(MAX) OCP levels are as follows:
TABLE 2.
RSET
()
OPEN
OCP (A) AT VIN = 12V,
PVCC = 5V
13.3
OCP (A) AT VIN = 12V
PVCC = 12V
17.3
50k
12.6
16.6
20k
11.4
14.9
10k
10.2
13.3
5k
7.6
10.3
3k
6.3
8.3
2k
4.9
6.7
The range of allowable voltages detected (2 x ISET x RSET) is
0mV to 475mV. If the voltage drop across RSET is set too low,
then this can cause almost continuous OCP tripping and retry.
It will also be very sensitive to system noise and in-rush current
spikes, so it should be avoided. The maximum usable setting is
around 0.2V across RSET (0.4V across the MOSFET); values
above this might disable the protection. Any voltage drop
across RSET that is greater than 0.3V (0.6V MOSFET trip
point) will disable the OCP. Note that conditions during power-
up or during a retry may look different than normal operation.
During power-up in a 12V system, the ISL8201M starts
operation just above 4V; if the supply ramp is slow, the soft-
start ramp might be over well before 12V is reached.
Therefore, with low-side gate drive voltages, the rDS(ON) of the
MOSFET will be higher during power-up, effectively lowering
the OCP trip. In addition, the ripple current will likely be
different at a lower input voltage. Another factor is the digital
nature of the soft-start ramp. On each discrete voltage step,
there is in effect, a small load transient and a current spike to
charge the output capacitors. The height of the current spike is
not controlled, however, it is affected by the step size of the
output and the value of the output capacitors, as well as the
internal error amp compensation. Therefore, it is possible to
trip the overcurrent with in-rush current, in addition to the
normal load and ripple considerations.
Figure 19 shows the output response during a retry of an
output shorted to PGND. At time t0, the output has been turned
off due to sensing an overcurrent condition. There are two
internal soft-start delay cycles (t1 and t2) to allow the MOSFETs
to cool down in order to keep the average power dissipation in
FN6657 Rev 3.00
October 28, 2014
retry at an acceptable level. At time t2, the output starts a
normal soft-start cycle, and the output tries to ramp. If the short
is still applied and the current reaches the ISET trip point any
time during the soft-start ramp period, the output will shut off
and return to time t0 for another delay cycle. The retry period is
thus two dummy soft-start cycles plus one variable one (which
depends on how long it takes to trip the sensor each time).
Figure 19 shows an example where the output gets about half-
way up before shutting down; therefore, the retry (or hiccup)
time will be around 17ms. The minimum should be nominally
13.6ms and the maximum 20.4ms. If the short condition is
finally removed, the output should ramp up normally on the
next t2 cycle.
t0
t1
t2
VOUT
FIGURE 19. OVERCURRENT RETRY OPERATION
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always enabled
during soft-start; once it trips, it will go into retry (hiccup) mode.
The retry cycle will always have two dummy time-outs, plus
whatever fraction of the real soft-start time passes before the
detection and shutoff. At that point, the logic immediately starts
a new two dummy cycle time-out.
Input Voltage Considerations
Figure 12 shows a standard configuration where PVCC is either
5V (±10%) or 12V (±20%). In each case, the gate drivers use
the PVCC voltage for low-side gate and high-side gate driver. In
addition, PVCC is allowed to work anywhere from 6.5V up to the
14.4V maximum. The PVCC range between 5.5V and 6.5V is
not allowed for long-term reliability reasons, but transitions
through it to voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias, which turns on
between 5.5V and 6.5V. Some of the delay after POR is there to
allow a typical power supply to ramp-up past 6.5V before the
soft-start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should be
minimal. Thus, while the recommendation is to not have the
output enabled during the transition through this region, it may
be acceptable. The user should monitor the output for their
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