UPSD3212A(2009) 查看數據表（PDF） - STMicroelectronics

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UPSD3212A
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

Architecture overview

UPSD3212A, UPSD3212C, UPSD3212CV

2.2.4

2.2.5

2.2.6

2.2.7

Program counter

The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL.

This counter indicates the address of the next instruction to be executed. In RESET state,

the program counter has reset routine address (PCH:00h, PCL:00h).

Program status word

The Program Status Word (PSW) contains several bits that reflect the current state of the

CPU and select Internal RAM (00h to 1Fh: Bank0 to Bank3). The PSW is described in

Figure 8. It contains the Carry flag, the Auxiliary Carry flag, the Half Carry (for BCD

operation), the General Purpose flag, the Register Bank Select flags, the Overflow flag, and

Parity flag.

[Carry flag, CY]. This flag stores any carry or not borrow from the ALU of CPU after an

arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.

[Auxiliary Carry flag, AC]. After operation, this flag is set when there is a carry from Bit 3 of

ALU or there is no borrow from Bit 4 of ALU.

[Register Bank Select flags, RS0, RS1]. These flags select one of four banks

(00~07H:bank0, 08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in Internal RAM.

[Overflow flag, OV]. This flag is set to '1' when an overflow occurs as the result of an

arithmetic operation involving signs. An overflow occurs when the result of an addition or

subtraction exceeds +127 (7Fh) or -128 (80h). The CLRV instruction clears the overflow

flag. There is no set instruction. When the BIT instruction is executed, Bit 6 of memory is

copied to this flag.

[Parity flag, P]. This flag reflects the number of Accumulator’s 1. If the number of

Accumulator’s 1 is odd, P=0; otherwise, P=1. The sum when adding Accumulator’s 1 to P is

always even.

Registers R0~R7

General purpose 8-bit registers that are locked in the lower portion of internal data area.

Data pointer register

Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This

register is used as a data pointer for the data transmission with external data memory in the

PSD module.

Figure 8. PSW (Program Status Word) register

MSB

PSW CY AC FO RS1 RS0 OV

Carry Flag

Auxillary Carry Flag

General Purpose Flag

LSB

P Reset Value 00h

Parity Flag

Bit not assigned

Overflow Flag

Register Bank Select Flags

(to select Bank0-3)

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