UPSD3212A(2009) 查看數據表（PDF） - STMicroelectronics

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UPSD3212A
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

UPSD3212A, UPSD3212C, UPSD3212CV

Architecture overview

2.3

Program memory

The program memory consists of two Flash memories: the main Flash memory (64 Kbit)

and the Secondary Flash memory (16 Kbit). The Flash memory can be mapped to any

address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data

memory space during Flash memory update or programming.

After reset, the CPU begins execution from location 0000h. As shown in Figure 9, each

interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to

jump to that location, where it commences execution of the service routine. External

Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be

used, its service routine must begin at location 0003h. If the interrupt is not going to be

used, its service location is available as general purpose Program Memory.

The interrupt service locations are spaced at 8-byte intervals: 0003h for External Interrupt 0,

000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an

interrupt service routine is short enough (as is often the case in control applications), it can

reside entirely within that 8-byte interval. Longer service routines can use a jump instruction

to skip over subsequent interrupt locations, if other interrupts are in use.

2.4

Data memory

The internal data memory is divided into four physically separated blocks: 256 bytes of

internal RAM, 128 bytes of Special Function Registers (SFRs) areas and 2 Kbytes (XRAM-

PSD) in the PSD module.

2.5

RAM

Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM

area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32

through 47, contain 128 directly addressable bit locations. The stack depth is only limited by

the available internal RAM space of 256 bytes.

Figure 9. Interrupt location of program memory

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Interrupt

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Location

Reset

008Bh

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0013h

000Bh

8 Bytes

0003h

0000h

AI06640

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