UPSD3212A(2009) 查看數據表（PDF） - STMicroelectronics
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UPSD3212A
(Rev.:2009)
(Rev.:2009)
STMicroelectronics
UPSD3212A Datasheet PDF : 181 Pages
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Architecture overview
UPSD3212A, UPSD3212C, UPSD3212CV
2.6
XRAM-PSD
The 2 Kbytes of XRAM-PSD resides in the PSD module and can be mapped to any address
space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development
tool.
2.7
SFR
The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15
gives an overview of the Special Function Registers. Sixteen address in the SFRs space are
both-byte and bit-addressable. The bit-addressable SFRs are those whose address ends in
0h and 8h. The bit addresses in this area are 80h to FFh.
Table 3. RAM address
Byte address
(in hexadecimal)
¯
FFh
30h
MSB
2Fh
7F
7E
Bit address (hex)
7D
7C
7B
7A
2Eh
77
76
75
74
73
72
2Dh
6F
6E
6D
6C
6B
6A
2Ch
67
66
65
64
63
62
2Bh
5F
5E
5D
5C
5B
5A
2Ah
57
56
55
54
53
52
29h
4F
4E
4D
4C
4B
4A
28h
47
46
45
44
43
42
27h
3F
3E
3D
3C
3B
3A
26h
37
36
35
34
33
32
25h
2F
2E
2D
2C
2B
2A
24h
27
26
25
24
23
22
23h
1F
1E
1D
1C
1B
1A
22h
17
16
15
14
13
12
21h
0F
0E
0D
0C
0B
0A
20h
07
06
05
04
03
02
1Fh
Register bank 3
18h
17h
Register bank 2
10h
0Fh
Register bank 1
08h
07h
Register bank 0
00h
Byte address
(in decimal)
¯
255
48
LSB
79
78
47
71
70
46
69
68
45
61
60
44
59
58
43
51
50
42
49
48
41
41
40
40
39
38
39
31
30
38
29
28
37
21
20
36
19
18
35
11
10
34
09
08
33
01
00
32
31
24
23
16
15
8
7
0
20/181
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