STK15C68(2011) 查看數據表（PDF） - Cypress Semiconductor
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STK15C68 Datasheet PDF : 17 Pages
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STK15C88
SRAM Write Cycle
Parameter
25 ns
45 ns
Cypress
Parameter
Alt
Description
Unit
Min Max Min Max
tWC
tAVAV
Write Cycle Time
25
45
ns
tPWE
tWLWH, tWLEH
Write Pulse Width
20
30
ns
tSCE
tELWH, tELEH
Chip Enable To End of Write
20
30
ns
tSD
tDVWH, tDVEH
. tHD
tWHDX, tEHDX
ly tAW
tAVWH, tAVEH
n tSA
tAVWL, tAVEL
o tHA
s tHZWE [7,8]
am tLZWE [7]
tWHAX, tEHAX
tWLQZ
tWHQX
gr Switching Waveforms
tion pro ADDRESS
ns. duc CE
desiging pro WE
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
10
15
0
0
20
30
0
0
0
0
10
15
5
5
Figure 7. SRAM Write Cycle 1: WE Controlled [8]
tWC
tSCE
tHA
tAW
tSA
tPWE
for newt ongo DATAIN
ed ppor DATA OUT
commteionnd to su ADDRESS
PREVIOUS DATA
tHZWE
tSD
tHD
DATA VALID
HIGH IMPEDANCE
Figure 8. SRAM Write Cycle 2: CE Controlled [8]
tWC
tLZWE
ot re oduc tSA
tSCE
tHA
r CE
N In p tAW
ns
ns
ns
ns
ns
ns
ns
WE
tPWE
DATA IN
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than VIH during address transitions.
Document Number: 001-50593 Rev. *C
Page 10 of 17
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