CY7C1399BN 查看數據表（PDF） - Cypress Semiconductor
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CY7C1399BN Datasheet PDF : 8 Pages
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CY7C1399BN
Capacitance[4]
Parameter
CIN: Addresses
CIN: Controls
COUT
Description
Input Capacitance
Output Capacitance
AC Test Loads and Waveforms[5]
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
5
pF
6
pF
6
pF
3.3V
OUTPUT
INCLUDING CL
JIG AND
SCOPE
R1 317Ω
R2
351Ω
3.0V
10%
GND
≤ 3 ns
ALL INPUT PULSES
90%
90%
10%
≤ 3 ns
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics Over the Operating Range[5]
-12
-15
-20
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
12
15
20
ns
tAA
Address to Data Valid
12
15
20
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE LOW to Data Valid
12
15
20
ns
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
5
6
7
ns
0
0
0
ns
5
6
6
ns
3
3
3
ns
6
7
7
ns
tPU
CE LOW to Power-Up
0
0
0
ns
tPD
CE HIGH to Power-Down
Write Cycle[8, 9]
12
15
20
ns
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE LOW to Write End
8
10
12
ns
tAW
Address Set-Up to Write End
8
10
12
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
8
10
12
ns
tSD
Data Set-Up to Write End
7
8
10
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[8]
WE HIGH to Low Z[6]
0
0
0
ns
7
7
7
ns
3
3
3
ns
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and capacitance CL = 30 pF.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06490 Rev. *A
Page 3 of 8
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