CXG1010N 查看數據表（PDF） - Sony Semiconductor
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CXG1010N Datasheet PDF : 6 Pages
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Block Diagram
VDD1 VDD2 VDD3
RFIN
RFOUT
VGG1
VCTL VGG2
Gate adjustment pin
Gate adjustment pin
VGG2
470Ω
680Ω
VGG1
Pin Configuration
GND
RFOUT
GND
VGG2
GND
VCTL
VGG1
GND
16
CXG1010N
VDD3
GND
VDD2
GND
VDD1
GND
RFIN
GND
1
Recommended Current Adjustment Method
(1) VGG2/PIN separate adjustment
(VGG2 adjustment 1)
(PIN adjustment 1)
When the RF input
(PIN) is off, the current
consumption (IDD) is
adjusted to 200 mA.
The output power
(POUT) is adjusted
to 21.5 dBm.
Variation of IDD and
POUT due to adjustment
IDD=200±20 mA
POUT=21.5 dBm
(VGG2 adjustment 2)
The current
consumption (IDD)
is finely adjusted to
200 mA.
IDD=200 mA
POUT=21.5±0.2 dBm
(PIN adjustment 2)
The output power
(POUT) is finely
adjusted to 21.5 dBm.
IDD=200±5 mA
POUT=21.5 dBm
(2) Simple adjustment
(IDD read)
When the RF input (PIN)
is off, the gate voltage
(VGG2) is set to 0.4 V
and it is read.
Variation of IDD and POUT
due to adjustment
(VGG2 setting)
The formula∗1 where
VGG2=f (IDD: VGG2=0.4 V)
is used to set VGG2.
∗1 e.g. VGG2=a-b x IDD
(PIN adjustment)
The output power (POUT)
is adjusted to 21.5 dBm.
IDD=200±5 mA
POUT=21.5 dBm
—2—
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