PACVGA201 查看數據表（PDF） - ON Semiconductor

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PACVGA201

VGA Port Companion Circuit

ON Semiconductor 

PACVGA201

SPECIFICATIONS (Cont’d)

Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)

Symbol

Parameter

Conditions

ICC1

ICC3

VCC1 Supply Current

VCC3 Supply Current

VCC1 = 5.0 V

VCC3 = 5 V, SYNC Inputs at GND

or VCC3, PWR_UP pin at VCC3,

SYNC Outputs Unloaded

VCC3 = 5 V, SYNC Inputs at 3.0 V,

PWR_UP Pin at VCC3, SYNC

Outputs Unloaded

VCC3 = 5 V, PWR_UP Input at

GND, SYNC Outputs Unloaded

VCC2 VCC2 Pin Open Circuit Voltage

VCC2 Voltage Internally Derived

from VCC3 via Diode D1,

No External Current Drawn

VIH

VIL

VOH

VOL

RB, RP

IIN

Logic High Input Voltage

Logic Low Input Voltage

Logic High Output Voltage

Logic Low Output Voltage

Resistor Value

Input Current

VIDEO_x Pins

HSYNC, VSYNC Pins

VCC3 = 5 V (Note 2)

VCC3 = 5 V (Note 2)

IOH = −4 mA, VCC3 = 5.0 V (Note 3)

IOL = 4 mA, VCC3 = 5.0 V (Note 3)

PWR_UP = VCC3 = 5.0 V

VCC1 = 5.0 V, VIN = VCC1 or GND

VCC3 = 5.0 V, VIN = VCC3 or GND

Min

Typ

Max

10

10

200

10

[VCC3 − 0.80]

2.0

0.8

4.4

0.4

0.5

1

2

1

1

Units

mA

mA

mA

mA

V

V

V

V

V

MW

mA

CIN

Input Capacitance on

VIDEO_1, VIDEO_2 and VIDEO_3 VCC1 = 5.0 V, VIN = 2.5 V,

Pins

Measured at 1 MHz

VCC1 = 2.5 V, VIN = 1.25 V,

Measured at 1 MHz

pF

4

4.5

tPLH

SYNC Buffer L  H Propagation Delay CL = 50 pF, VCC3 = 5.0 V,

Input tR and tF  5 ns

8

12

ns

tPHL

SYNC Buffer H  L Propagation Delay CL = 50 pF, VCC3 = 5.0 V,

Input tR and tF  5 ns

8

12

ns

tR, tF

SYNC Buffer Output Rise & Fall Times CL = 50 pF, VCC3 = 5.0 V,

Input tR and tF  5 ns

7.0

ns

VESD ESD Withstand Voltage

VCC1 = VCC2 = VCC3 = 5 V (Note 4)

8

kV

1. All parameters specified over standard operating conditions unless otherwise noted.

2. These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.

3. These parameters apply only to SYNC_OUT1 and SYNC_OUT2.

4. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC2 and VCC3 must be bypassed to GND

via a low impedance ground plane with a 0.2 mF or greater, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied

between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2,

VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard

2 kV per the Human Body model (MIL−STD−883, Method 3015).

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