PACVGA201 查看數據表（PDF） - ON Semiconductor

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PACVGA201

VGA Port Companion Circuit

ON Semiconductor 

H−Sync

V−Sync

DDC_Data

DDC_Clk

Red

Green

Blue ÎÎÎÎÎÎÎÎÎÎÎÎ

PACVGA201

APPLICATION INFORMATION

To Video

DAC VCC

0.2 mF 0.2 mF

5V

0.2 mF

2

VCC1

11

SYNC_IN1

13

SYNC_IN2

10

DDC_OUT2

9

DDC_OUT1

8

VCC2

1

VCC3

6

GND

7

PWR_UP

GND

PACVGA201

12

SYNC_OUT1

SYNC_OUT2 14

3

4 VIDEO_1

5 VIDEO_2

VIDEO_3

15

SD1 16

SD2

ÎÎÎÎÎÎÎÎÎ

H−Sync

V−Sync

DDC_Data

DDC_Clk

Red

Green

Blue

VF** − VIDEO EMI Filter

SF** − SYNC EMI Filter

Figure 1. Typical Connection Diagram

A resistor may be necessary between the VCC2 pin and ground if protection against a stream of ESD pulses is required while

the PACVGA201 is in the power−down state. The value of this resistor should be chosen such that the extra charge deposited

into the VCC2 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD

repetition rate specified by the IEC−61000−4−2 standard is one pulse per second. When the PACVGA201 is in the power−up

state, an internal discharge resistor is connected to ground via a FET switch for this purpose.

For the same reason, VCC1 and VCC3 may also require bypass capacitor discharging resistors to ground if there are no other

components in the system to provide a discharge path to ground.

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