AS6C1008L 查看數據表（PDF） - Alliance Semiconductor
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AS6C1008L Datasheet PDF : 15 Pages
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AS6C1008L
128k x 8 BIT SUPER LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Address
Dout
tRC
tAA
Previous Data Valid
tOH
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
Address
CE#
CE2
tRC
tAA
tACE
OE#
Dout
High-Z
tOE
tOLZ
tCLZ
tOH
tOHZ
tCHZ
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Confidential
- 6/15 -
Rev.2.a April 2016
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