WM8199 查看數據表（PDF） - Cirrus Logic

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WM8199

20MSPS 16-bit CCD Digitiser

Cirrus Logic 

WM8199

OVERALL SIGNAL FLOW SUMMARY

Figure 16 represents the processing of the video signal through the WM8199.

Production Data

INPUT

SAMPLING OFFSET DAC PGA

BLOCK

BLOCK BLOCK

V1

V2

V3

VIN

+-

++

X

analog

CDS = 1

VRESET

CDS = 0

PGA gain

A = 208/(283-PGA[7:0])

ADC BLOCK

OUTPUT

INVERT

BLOCK

+0

x (65535/VFS)

if PGAFS[1:0]=11

D1

+65535 if PGAFS[1:0]=10

+32768 if PGAFS[1:0]=0x digital

D2

OP[7:0]

D2 = D1 if INVOP = 0

D2 = 65535-D1 if INVOP = 1

VVRLC

VRLCEXT=1 VRLCEXT=0

Offset 260mV*(DAC[7:0]-127.5)/127.5

DAC

VIN is RINP or GINP or BINP

VRESET is VIN sampled during reset clamp

VRLC is voltage applied to VRLC pin

RLC See parametrics for

DAC DAC voltages.

CDS, VRLCEXT,RLCV[3:0], DAC[7:0],

PGA[7:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS=1 for CDS, 0 for non-CDS

Figure 16 Overall Signal Flow

The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the

difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the

difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,

optionally set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

black level of the input signal towards 0V, producing V2.

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

outputting voltage V3.

The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.

The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the processing of the video and reset level signals through

the WM8199. The Values of V1 V2 and V3 are often calculated in reverse order during device

setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then

adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is

set to position the reset level correctly during operation.

Note: Refer to WAN0123 for detailed information on device calibration procedures.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the

input video.

V1

=

VIN - VRESET ................................................................... Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

V1

=

VIN - VVRLC .................................................................... Eqn. 2

If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.

If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.

VVRLC =

(VRLCSTEP ∗ RLCV[3:0]) + VRLCBOT ................................. Eqn. 3

VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.

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PD, Rev 4.4, July 2008

17

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